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IPQ5322 BLSP Channel Allocation
Interface Name | TX Channel | RX Channel | Interrupt |
---|
BLSP_BLSP_UART0 | 0 | 1 | 290 |
BLSP_BLSP_UART1 | 2 | 3 | 291 |
BLSP_BLSP_QUP0 | 4 | 5 | 292 |
BLSP_BLSP_QUP1 | 6 | 7 | 293 |
BLSP_BLSP_QUP2 | 8 | 9 | 294 |
IPQ5322 BLSP GPIO Mapping
GPIO# | Func Sel # 1 | Func Sel # 2 | Func Sel # 3 | Func Sel # 4 | Func Sel # 5 |
---|
14 | blsp0_spi_clk | blsp1_uart_rfr_n[0] | | | |
15 | blsp0_spi_mosi | blsp1_uart_tx[0] | | | |
16 | blsp0_spi_miso | blsp0_i2c_scl | blsp1_uart_rx[0] | | |
17 | blsp0_spi_cs_n | blsp0_i2c_sda | blsp1_uart_cts_n[0] | | |
18 | blsp0_uart_rx[0] | | | | |
19 | blsp0_uart_tx[0] | | | | |
25 | | blsp1_uart_rx[1] | blsp1_spi_mosi[1] | | |
26 | | blsp1_uart_rfr_n[1] | blsp1_spi_cs_n[1] | | |
27 | | blsp0_uart_tx[1] | blsp1_uart_tx[1] | blsp1_spi_clk[1] | |
28 | | blsp0_uart_rx[1] | blsp1_uart_cts_n[1] | blsp1_spi_miso[1] | |
29 | | blsp1_spi_mosi[0] | blsp1_i2c_scl[0] | | |
30 | | blsp1_spi_cs_n[0] | blsp1_i2c_sda[0] | | |
31 | | blsp1_spi_miso[0] | | | |
32 | | blsp1_spi_cIk[0] | | | |
33 | | blsp1_uart_tx[2] | blsp2_i2c_sc[1] | blsp2_spi_clk[0] | |
34 | | blsp1_uart_rfr_n[2] | blsp2_i2c_sda[1] | blsp2_spi _mosi[0] | |
35 | | blsp1_uart_rx[2] | | | blsp2_spi miso[0] |
36 | | blsp1_uart_cts_n[2] | | | blsp2_spi_cs_n[0] |
37 | | blsp2_spi_cs1_n | | | |
40 | | blsp1_i2c_sc[1] | blsp2_spi_miso[1] | | |
41 | | blsp1_i2c_sda[1] | blsp2_spi_mosi[1] | | |
42 | | blsp2_spi _cIk[1] | | | |
43 | | | | blsp2_i2c_scl[0] | |
45 | | | | blsp2_i2c_sda[0] | |
52 | | blsp2_spi _cs_n[1] | | | |